Xilinx Design Summary

CALENDAR200708 Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	404	9,312	4%
Number of 4 input LUTs	1,918	9,312	20%
Logic Distribution
Number of occupied Slices	1,079	4,656	23%
Number of Slices containing only related logic	1,079	1,079	100%
Number of Slices containing unrelated logic	0	1,079	0%
Total Number of 4 input LUTs	2,046	9,312	21%
Number used as logic	1,918
Number used as a route-thru	128
Number of bonded IOBs	23	232	9%
IOB Flip Flops	3
Number of GCLKs	2	24	8%
Total equivalent gate count for design	19,348
Additional JTAG gate count for IOBs	1,104

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met